The present invention relates to an A/D converter for converting analog signals to digital signals, and in particular to a pipelined A/D converter having a cascade connection of A/D-D/A sub-blocks respectively for determining partial bits of a conversion output.
Conventionally, as an A/D converter for realizing a high-speed conversion rate, a flash-type A/D converter is known. This A/D converter has 2n voltage comparators (where n is the number of output bits) and all output bits are determined simultaneously.
An example of an A/D converter having a conversion rate comparable to that of the flash-type A/D converter and reduced in circuit size and power dissipation is described in 1987 IEEE International Solid-State Circuits Conference, pp. 210-211. This A/D converter is called "pipelined A/D converter" and has a cascade connection of a plurality of A/D-D/A sub-blocks each having a flash-type A/D converter with a small number of bits. An A/D-D/A sub-block of a first stage determines several high-order bits of the output, inversely converts that conversion output to an analog signal, derives a difference (conversion residue) between the resultant analog signal and the input analog signal before conversion, amplifies the difference, and transfers the amplified difference to an A/D-D/A sub-block of a succeeding stage. The A/D-D/A sub-block of the succeeding stage performs A/D conversion on the transferred signal, determines several succeeding bits, and performs inverse conversion, derivation of a residue signal and amplification. By connecting a plurality of A/D-D/A sub-block stages in a cascade form and disposing a sample-and-hold circuit for the A/D conversion input of each stage, conversion processing is advanced in a pipeline form every several bits from the higher order. In this pipelined A/D converter, the time taken for a certain analog value to be converted becomes the time required for that sample value to pass through all blocks. On the other hand, however, the conversion rate is determined substantially by the conversion time of each block and hence a comparatively high conversion rate can be attained. Further, as compared with a pipelined A/D converter having an enormous number of voltage comparators, the number of voltage comparators can be substantially reduced and power dissipation can be reduced.
Although a two-step parallel A/D converter described in U.S. Pat. No. 4,875,048 has two block stages, it has nearly the same structure as that of the above described pipelined A/D converter.